10.7916/D8Q81MZP
The Benefits of Using Clock Gating in the Design of Networks-on-Chip
Columbia University
2011
2017-06-16
2018-08-30
Petracca, Michele
Carloni, Luca
Computer science
Columbia University. Computer Science
Reports
Networks-on-chip (NoC) are critical to the design of complex multi-core system-on-chip (SoC) architectures. Since SoCs are characterized by a combination of high performance requirements and stringent energy constraints, NoCs must be realized with low-power design techniques. Since the use of semicustom design flow based on standard-cell technology libraries is essential to cope with the SoC design complexity challenges under tight time-to-market constraints, NoC must be implemented using logic synthesis. In this paper we analyze the major power reduction that clock gating can deliver when applied to the synthesis of a NoC in the context of a semi-custom automated design flow.