10.15480/882.2018
Ranjan, Rajeev
Rajeev
Ranjan
1179465601
Mendoza Ponce, Pablo
Pablo
Mendoza Ponce
0000-0003-1048-577X
1179466446
Hellweg, Wolf Lukas
Wolf Lukas
Hellweg
1179487001
Kyrmanidis, Alexandros
Alexandros
Kyrmanidis
1179487214
Abu Saleh, Lait
Lait
Abu Saleh
0000-0001-5891-3628
1081396180
Schroeder, Dietmar
Dietmar
Schroeder
131458132
Krautschneider, Wolfgang H.
Wolfgang H.
Krautschneider
0000-0001-8629-4545
102432267X
Integrated circuit with memristor emulator array and neuron circuits for biologically inspired neuromorphic pattern recognition
World Scientific Publishing
2017
ASIC
emulator
CMOS
LTD
LTP
memristor
neuron
synaptic plasticity
pattern recognition
Biowissenschaften, Biologie
TUHH Universitätsbibliothek
TUHH Universitätsbibliothek
2019-02-28
2019-02-28
2017-04-27
en
Journal Article
Journal of Circuits, Systems and Computers 11 (26): 1750183 (2017)
http://hdl.handle.net/11420/2021
urn:nbn:de:gbv:830-882.026562
10.15480/882.2018
10.1142/S0218126617501833
https://creativecommons.org/licenses/by/4.0/
This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99μs (200kOhm) to 204.8MOhm)) and other four having conductance ranging from 195ns to 190μs (5.2kOhm) to 5.12MOhm)). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process.
Deutsche Forschungsgemeinschaft (DFG)
KR 3281/8-3
FOR 2093: Memristive Bauelemente für neuronale Systeme, Teilprojekt C2 "Neuronale Schaltungen"
0218-1266
Journal of circuits, systems, and computers
2017
World Scientific Publishing